system verilog - How to send data over AXI Stream using Xiling VIP IP -


i'm trying use axi stream verification ip cannot figure out how use in slave mode. how can data out of agent:

import axi4stream_vip_v1_0_1_pkg::*; import axis_vip_master_pkg::*; import axis_vip_slave_pkg::*;  module shift_register_vip();     logic aclk;     logic aresetn;     logic [63:0] in_tdata;     logic        in_tvalid;     logic        in_tready;     logic [23:0] out_tdata;     logic        out_tvalid;     logic        out_tready;      axis_vip_master vip_master(.aclk(aclk), .aresetn(aresetn), .m_axis_tdata(in_tdata), .m_axis_tvalid(in_tvalid), .m_axis_tready(in_tready));     shift_register dut(.aclk(aclk), .aresetn(aresetn), .s_axis_data(in_tdata), .s_axis_valid(in_tvalid), .s_axis_ready(in_tready), .m_axis_data(out_tdata), .m_axis_valid(out_tvalid), .m_axis_ready(out_tready));     axis_vip_slave vip_slave(.aclk(aclk), .aresetn(aresetn), .s_axis_tdata(out_tdata), .s_axis_tvalid(out_tvalid), .s_axis_tready(out_tready));      initial aclk = 1;     #5ns aclk <= ~aclk;      axis_vip_master_mst_t master_agent;     axis_vip_slave_slv_t slave_agent;      mailbox mbx;     mailbox sbx;      task generator();         (int = 0; < 255; i++) begin             logic [7:0] word = $random();             mbx.put(word);             sbx.put(word);         end     endtask      task run_master();         while (1) begin             axi4stream_transaction trans = master_agent.driver.create_transaction();             logic [63:0] din;             (int = 0; < 8; i++) begin                 mbx.get(din[i * 8 +: 8]);             end             trans.set_data_beat(din);             master_agent.driver.send(trans);         end     endtask      initial begin         master_agent = new("master", vip_master.inst.if);         slave_agent = new("slave", vip_slave.inst.if);         mbx = new();         sbx = new();         master_agent.start_master();         slave_agent.start_slave();         aresetn <= 0;         repeat (4) @(posedge aclk);         aresetn <= 1;         fork             generator();             run_master();         join     end endmodule


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